Boolean Algebra

Main Page :: Boolean Algebra

Boolean Algebra

These are the various 'logic gates' used to create all computer logic. At their core, they are all made up of the 'NAND' gate.

Logic Gates

Logic gates can be represented by showing two input lines and one output line followed by a table showing what electrical/binary state the inputs must be in to effect a certain output state. In these 'Truth Tables', the two inputs are represented as inputs 'A' and 'B', and the output is represented by 'Y'.

In real terms, a signal state of "true" is achieved when the voltage on the line goes above a certain threshold voltage and can be represented as a binary '1' or described as being 'high'. Conversely, a signal state of "false" is achieved when the voltage on the line goes below a certain threshold voltage and can be represented as a binary '0' or described as being 'low'.

A note of interest; Logic gates use a buffer space between the voltage states needed to determine a high or low state. This is the case so that slight variances in the line voltage won't change the value of line. For example, a 5 volt gate may require that the line voltage goes above 3.5 volts before a low signal is declared high. In turn, the signal will not go low again until the voltage drops to below 1.5 volts. This way, a small spike above 1.5 volts when the signal is low will not change it's value to high and a slight voltage dip below 3.5 volts will not drop a high signal to low.

AND

A and B must be true (1) for the output to be true (1). If either input is false (0), the output becomes (0).

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 0 |
 | 0 | 1 || 0 |
 | 1 | 0 || 0 |
 | 1 | 1 || 1 |
 +---+---++---+

NAND

• (Not AND)

A and B may not both be true (1) for the output to be true (1). If either input is false (0), the output becomes (1). This is in direct opposition to the 'AND' gate.

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 1 |
 | 0 | 1 || 1 |
 | 1 | 0 || 1 |
 | 1 | 1 || 0 |
 +---+---++---+

OR

If A or B is true (1), the output becomes true (1).

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 0 |
 | 0 | 1 || 1 |
 | 1 | 0 || 1 |
 | 1 | 1 || 1 |
 +---+---++---+

NOR

• (Not OR)

When A nor B is true (1), the output will become true (1). This is in direct opposition to the 'OR' gate.

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 1 |
 | 0 | 1 || 0 |
 | 1 | 0 || 0 |
 | 1 | 1 || 0 |
 +---+---++---+

XOR

• (eXclusive OR)

If A or B is true (1) exclusively, the output becomes true (1). If both A and B become true, the output returns to '0'.

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 0 |
 | 0 | 1 || 1 |
 | 1 | 0 || 1 |
 | 1 | 1 || 0 |
 +---+---++---+

XNOR

• (eXclusive Not OR)

If A nor B is true (1) exclusively, the output becomes true (1). This is in direct opposition to the 'XOR' gate.

• Truth Table

 +---+---++---+
 | A | B || Y |
 +---+---++---+
 | 0 | 0 || 1 |
 | 0 | 1 || 0 |
 | 1 | 0 || 0 |
 | 1 | 1 || 1 |
 +---+---++---+

Inverter

Though not a typical logic gate, it is a very important gate just the same. It's purpose is to invert the input signal. So, if the input line is 'true', the output becomes 'false', and vice versa.

• Truth Table

 +---++---+
 | A || Y |
 +---++---+
 | 0 || 1 |
 | 1 || 0 |
 +---++---+

 

Any questions, feedback, advice, complaints or meanderings are welcome.
Us: Alteeve's Niche!	Support: Mailing List	IRC: #clusterlabs on Libera Chat
© Alteeve's Niche! Inc. 1997-2023		Anvil! "Intelligent Availability™" Platform
legal stuff: All info is provided "As-Is". Do not use anything here unless you are willing and able to take responsibility for your own actions.